The present invention relates generally to semiconductor devices and the process of their fabrication and more specifically to fabrication of an improved laterally dielectrically isolated surface region for use in fabricating selfaligned semiconductor devices.
Integrated circuits are generally fabricated as a multiplicity of interconnected devices such as diodes and transistors formed side by side within a monolithic body of semiconductor material often called a semiconductor wafer. To prevent unwanted interaction, it is common practice to provide some form of electrical isolation barrier between the devices. The isolation may be achieved by providing PN junctions between the devices which are readily reverse-biased to preclude current flow across the junction or include dielectric barriers.
While known PN junction isolation techniques have proven successful, they suffer certain disadvantages in that they severely limit the surface area of the semiconductor body available for device fabrication. Since the lateral isolation region is formed by diffusion, the impurities spread vertically and laterally inthe substrate. Thus, the PN junction spreads towards the devices which are to be isolated. It is essential that the isolation junction not come in contact with the device to be isolated, and therefore, sufficient space must be provided between devices to account for this lateral spreading.
Another known technique for device isolation, termed the Isoplanar technique involves the deposition of a silicon nitride film on the semiconductor surface, the etching of grooves through the film and into the semiconductor body, followed by thermal growth of silicon dioxide to fill the grooves. The silicon nitride film retards the growth of the oxide other than in the grooves. After the grooves are filled, the silicon nitride film is etched away to leave oxide isolated semiconductor islands with a planar surface. Since the grooves are filled with oxide by thermal oxidation, the depth of the grooves and consequently the thickness of the semiconductor layer to be isolated by the process are limited. Additionally, since the isolation region is formed by oxidation, the oxide-semiconductor boundary spreads vertically and laterally in the substrate towards the devices which are to be isolated.
A more desirable isolation technique, which can be termed Polyplanar, is described in U.S. Pat. No. 3,979,237 issued Sept. 7, 1976, to Morcom et al. According to the Polyplanar isolation technique a thin film of protective material is deposited on the planar surface of a semiconductor wafer in which integrated circuits are to be fabricated. A mask conforming to the desired isolation pattern is provided over the exposed surface of the protective thin film and isolation grooves are etched through the film and into the semiconductor material. The grooves are of a sufficient depth to define the regions within which devices are to be fabricated. An insulator layer such as a film of silicon dioxide is then formed over the surfaces of the grooves. The remaining portions of the grooves are then filled with pyrolytically deposited dielectric material or other fill material capable of withstanding subsequent high temperature processing to the level of the original planar surface of the semiconductor body. Due to limitations in the manufacturing process, the fill material will overfill the grooves and will coat surfaces other than the grooves themselves. The protective thin film functions to allow the excess fill material to be removed from the surface of the semiconductor wafer without damaging the underlying planar surface of the semiconductor material. After removal of the excess fill material, the thin film is removed by etching to expose a planar surface of isolated semiconductor islands. A full and complete description of this Polyplanar isolation process is given in the aforementioned patent to Morcom et al and the reader is directed to that patent for a full understanding of this isolation process.
A major disadvantage of the Polyplanar isolated substrate is the inability to use the isolation regions as a self-aligning region for the formation of doped regions in the substrate. A substrate isolated according to the process of the Morcom, et al., patent is illustrated in FIG. 1 as including a substrate 10, a buried layer 12, an epitaxial layer 14, and a groove 16 having an oxide layer 18 and polycrystalline material 20. By subsequent processing, an oxide layer 22 has been formed over the substrate having a thickness over the polycrystalline material 20 no greater than the thickness over the epitaxial regions 14. An opening 24 is formed in oxide layer 22 into which impurities are to be diffused to form a doped region or to which metal contact to the epitaxial regions 14 are to be formed. The opening 24 is formed using a photolithographic technique including an oxide etch. Because the oxide layer 22 is of equal thickness over the epitaxial layer 14 and the polycrystalline material 20, a slight over etch of the oxide layer 22 in the formation of opening 24 will remove a portion of oxide layer 18 exposed to the etching medium in opening 24. The inadvertent removal of a portion of oxide layer 18 at the surface of the structure will create a retrograde surface profile 26 where the upper corner of the polycrystalline is exposed by the etching of opening 24.
This retrograde surface profile 26 is undesirous and upon further oxidation will not be eliminated. Any subsequent metalization interconnect patterns formed by the evaporation, sputtering or other deposition techniques followed by a photolithographic operation will result in an undesirous cavity 28 in the metal layer as it passes over the retrograde surface profile 26. This results from the metal etch solution seeping laterally in the groove of the retrograde surface profile 26 and etching the metal cavity 28. Additionally, if the opening 24 is for the purpose of making contact to the epitaxial layer 14 by the metal layer, contact is inadvertently also made to the polycrystalline material 20. If opening 24 is for the purpose of forming a doped region in epitaxial layer 14, a doped region in the polycrystalline material 20 is simultaneously created which may not be desired. For instance, it may be desired to utilize the polycrystalline material as a resistive element having an impurity doping different from the doped semiconductor material.